1. Field of the Invention
The present invention generally relates to the field of computer graphics systems. More particularly, the present invention relates to rasterization and fill rate optimization within computer graphics systems.
2. Description of the Related Art
Modern graphics systems have been rapidly increasing their performance as the result of ever higher clock speeds and improved levels of integration. Smaller feature sizes on integrated circuits and higher clock frequencies have led to significant increases in the both number of triangles that may be rendered per frame and the number of frames that may be rendered per second.
However, new applications such as three-dimensional (3D) modeling, virtual reality, and 3D computer games continue to demand even greater performance from graphics systems. Thus, system designers have continued to improve performance throughout the entire graphics system pipeline to try and meet the performance needs of these new applications.
FIG. 1 illustrates one example of a generic graphics system, but numerous variations are possible and contemplated. As shown in the figure, the system is a pipeline in which graphics data is initially read from a computer system's main memory into the graphics system. The graphics data may include geometric primitives such as polygons, NURBS (Non-Uniform Rational B-Splines), sub-division surfaces, voxels (volume elements) and other types of data. The various types of data are typically converted into triangles (e.g., three vertices having at least position and color information). Then, transform and lighting calculation units 50 receive and process the triangles. Transform calculations typically include changing a triangle's coordinate axis, while lighting calculations typically determine what effect, if any, lighting has on the color of triangle's vertices. The transformed and lit triangles are then conveyed to a clip test/back face culling unit 52 that determines which triangles are outside the current parameters for visibility (e.g., triangles that are off screen). These triangles are typically discarded to prevent additional system resources from being spent on non-visible triangles.
Next, the triangles that pass the clip test and back-face culling are translated into screen space 54. The screen space triangles are then forwarded to the set-up and draw processor 56 for rasterization. Rasterization typically refers to the process of generating actual pixels by interpolation from the vertices. In some cases samples are generated by the rasterization process instead of pixels. A pixel typically has a one-to-one correlation with the hardware pixels present in a display device, while samples are typically more numerous than the hardware elements and need not have any direct correlation to the display device. Regardless of whether pixels or samples are used, once drawn they are stored into a frame buffer 58.
Next, the pixels are read from frame buffer 58 and converted into an analog video signal by digital-to-analog converters 60. If samples are used, the samples are read out of frame buffer 58 and filtered to generate pixels, which are stored and later conveyed to digital to analog converters 60. The video signal from converters 60 is conveyed to a display device 62 such as a computer monitor, LCD display, or projector.
As noted above, many applications place great demands on graphics systems. In some graphics systems, the rasterization algorithm is configured to calculate multiple pixels/samples per clock cycle called “tiles”. Unfortunately, this can lead to less than ideal datapath utilization due to an effect called fragmentation. Fragmentation occurs when a portion of the rasterization hardware is assigned to areas outside of the geometry currently being rasterized. For example, a rasterization algorithm that calculates tiles of two horizontally adjacent pixels per cycle may experience fragmentation when the geometry being rasterized has an odd width in pixels. The last cycle of rasterization on an odd width will have only one pixel to calculate. The adjacent pixel, being outside of the current geometry, will not be rendered. This causes an inefficiency as subsequent hardware in the pipeline will be unused for this tile's missing or disabled pixel. Thus, a system and method capable of improving fill rate performance with respect to fragmentation is desired.